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data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 1024mb ddr3 C sdram u dimm 240 pin u dimm sgu01g64a1b g 1 sa - xx r 1gbyte in fbga techn ology rohs compliant the refresh rate has to be doubled when 85c data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 this swissbit module is an industry standard 240 - pin 8 - byte ddr3 sdram dual - in - line memory module ( u dimm) which is organized as x64 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and c k#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst len gth is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial presence detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timin g parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. column addr. refresh module bank select 128m x 64bit 8 x 128m x 8bit ( 1024m bit) 14 ba0, ba1, ba2 10 8k s0# module dimensions in mm 133.35 (long) x 30(high) x 2.70 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sgu01g64a1b g 1 sa - bb r 1024 mb 8.5 gb/s 1.87ns/1066mt/s 7 - 7 - 7 sgu01g64a1b g 1 sa - cc r 1024 mb 10.6 gb/s 1.5ns/1333mt/s 9 - 9 - 9 sgu01g64a1bg1sa - dcr 1024 mb 12.8 gb/s 1.25ns/1600mt/s 11 - 11 - 11 pin name a0 C a9 , a11 C a13 address inputs a10/ap address input / autoprecharge bit ba0 C ba2 bank address inputs dq0 C dq63 data input / output dm0 C dm7 input data mask dqs0 C dqs7 data strobe, positive line dqs0# - dqs7# data strobe, negative line (only used when differential data strobe mode is enabled) s0# chip select ras# row address strobe cas# column address strobe we# write enable cke 0 cl ock enable figure 1: mechanical d imensions
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 odt0 on - die termination ck0 clock inputs, positive line ck0# clock inputs, negative line v dd supply voltage (1.5v 0.075v) v ref dq reference voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs nc no connectio n pin configuration frontside pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref dq 27 dq18 49 nc (v tt ) 75 v dd 101 v ss 2 v ss 28 dq19 50 cke0 76 nc( s1# ) 102 dqs6# 3 dq0 29 v ss 51 v dd 77 nc( odt1 ) 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 nc( err_out# ) 79 nc( s2# ) 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 34 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 d q27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v dd 86 v ss 112 dqs7 13 dq9 39 nc( cb0 ) 61 a2 87 dq34 113 v ss 14 v ss 40 nc( cb1 ) 62 v dd 88 dq35 114 dq58 15 dqs1# 41 v ss 63 nc( ck1 ) 89 v ss 115 dq59 16 dqs1 42 nc( dqs8# ) 64 nc( ck1# ) 90 dq40 116 v ss 17 v ss 43 n c( dqs8 ) 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 nc( cb2 ) 67 v ref ca 93 dqs5# 119 sa2 20 v ss 46 nc( cb3 ) 68 nc( par_in ) 94 dqs5 120 v tt 21 dq16 47 v ss 69 v dd 95 v ss 22 dq17 48 nc (v tt ) 70 a10/ ap 96 dq42 23 v ss 71 ba0 9 7 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas# 100 dq49 signals in brackets () may be connected at the dimm socket, but are not used on the dimm
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 backside pin symbol pin symbol pin symbol pin symbol pin symbol 12 1 v ss 147 dq23 169 nc( cke1 ) 195 odt0 221 dm6( dqs15 ) 122 dq4 148 v ss 170 v dd 196 a13 222 nc( dqs15# ) 123 dq5 149 dq28 171 nc( a15 ) 197 v dd 223 v ss 124 v ss 150 dq29 172 nc( a14 ) 198 nc( s3# ) 224 dq54 125 dm0( dqs9 ) 151 v ss 173 v dd 199 v ss 225 dq55 126 nc( dqs 9# ) 152 dm3( dqs12 ) 174 a12/ bc # 200 dq36 226 v ss 127 v ss 153 nc( dqs12# ) 175 a9 201 dq37 227 dq60 128 dq6 154 v ss 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 dm4( dqs13 ) 229 v ss 130 v ss 156 dq31 178 a6 204 nc( dqs13# ) 230 dm7( dqs16 ) 131 dq12 157 v ss 179 v dd 205 v ss 231 nc( dqs16# ) 132 dq13 158 nc( cb4 ) 180 a3 206 dq38 232 v ss 133 v ss 159 nc( cb5 ) 181 a1 207 dq39 233 dq62 134 dm1( dqs10 ) 160 v ss 182 v dd 208 v ss 234 dq63 135 nc( dqs10# ) 161 dm8( dqs17 ) 183 v dd 209 dq44 235 v ss 136 v ss 162 nc( dqs17# ) 184 ck0 210 dq45 236 v ddspd 137 dq14 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 nc( cb6 ) 186 v dd 212 dm5( dqs14 ) 238 sda 139 v ss 165 nc( cb7 ) 187 nc (event#) 213 nc( dqs14# ) 239 v ss 140 dq20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 2 15 dq46 142 v ss 168 reset# 190 ba1 216 dq47 143 dm2( dqs11 ) 191 v dd 217 v ss 144 nc( dqs11# ) 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss signals in brackets () may be connected at the dimm socket, but are no t used on the dimm
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 functional block diagramm 1024mb ddr3 sdram dimm, 1 rank and 8 components i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 7 v refdq v refca d 0 - d 7 d 0 - d 7 d 0 - d 7 v ss ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 7 a 0 - a 13 a 0 - a 13 : sdram d 0 - d 7 ras ras : sdram d 0 - d 7 cas cas : sdram d 0 - d 7 we we : sdram d 0 - d 7 odt 0 odt : sdram d 0 - d 7 cke 0 cke : sdram d 0 - d 7 ck 0 ck : sdram d 0 - d 7 ck 0 ck : sdram d 0 - d 7 reset reset : sdram d 0 - d 7 notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details .
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v v dd l supply voltage v dd l - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 i dd specifications and conditions (0c t case + 85c, v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 12800 - cl11 10600 - cl9 8500 - cl7 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 280 280 280 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 360 336 320 ma precharge power - down current: all device banks idle; p ower - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 96 96 96 ma slow exit 80 80 80 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); ck e is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 120 120 120 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 120 120 120 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are fl oating at v ref (always fast exit) i dd3p 120 120 120 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 160 160 160 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 600 520 440 ma
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 parameter & test condition symb ol max. unit 12800 - cl11 10600 - cl9 8500 - cl7 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 640 560 480 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# i s high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 720 720 680 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 80 80 80 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1024 1000 800 ma *) value calculated as one mod ule rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 - cl11 10600 - cl9 8500 - cl7 unit cl (i dd ) 11 9 7 t ck t rcd (i dd ) 13.75 13.5 13.125 ns t rc (i dd ) 48.75 49.5 50.625 ns t rrd (i dd ) 6.25 6 7.5 ns t ck (i dd ) 1.25 1.5 1.87 ns t ras min (i dd ) 35 36 37.5 ns t ras max (i dd ) 70200 70200 70200 ns t rp (i dd ) 13.75 13.5 13.125 ns t rfc (i dd ) 110 110 110 ns
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical charac teristics and recommended ac operating conditions (0c t case , + 85c, v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 - cl11 10600 - cl9 8500 - cl 7 parameter symbol min max min max min max unit clock cycle time cl = 11 t ck (11) 1.25 1.5 - - - - ns cl = 10 t ck (10) 1.5 <1.8 75 1.5 <1.875 - - cl = 9 t ck (9) 1.5 <1.875 1.5 <1.875 - - cl = 8 t ck (8) 1.875 <2.5 1.875 <2.5 - - cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 1.875 <2.5 cl = 6 t ck (6) 2.5 3.3 2.5 3.3 2.5 3.3 cl = 5 t ck (5) 3.0 3.3 3.0 3.3 3.0 3.3 read cmd to 1 st data t aa 13.75 - 13.5 - 13.125 - ck high - level width t ch 0.47 0.53 0.47 0.53 0.47 0.53 t ck ck low - level width t cl 0.47 0.53 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 225 - 0.25 - 0.3 ns data - out low - impedance window from ck/ck# t lz - 450 225 - 0.5 0.25 - 0.6 0.3 ns dq and dm input setup time relative to dqs t ds(base) - - 30 - 25 - ps dq and dm input hold time relative to dqs t dh(base) - - 65 - 100 - ps dq and dm input setup time relative to dqs v ref =1v/ns t ds1v 160 - 180 - 200 - ps dq and dm input hold time r elative to dqs v ref =1v/ns t dh1v 145 - 165 - 200 - ps dq and dm input pulse width ( for each input ) t dipw 360 - 0.4 - 0.49 - ns dqs, dqs# to dq skew, per access t dqsq - 100 - 125 - 150 ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - 0.38 - t ck (av g) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0. 55 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 225 225 - 255 +255 - 300 300 ps dqs, dqs# rising to/from ck, ck# when dll disabled t dqsck dll_dis 1 10 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0.18 - 0.2 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0.18 - 0.2 - 0.2 - t ck dqs read preamble t rpre 0.9 note1 0.9 note1 0.9 note1 t ck dqs read postamble t rpst 0.3 note2 0.3 note2 0.3 note2 t ck dqs wri te preamble t wpre 0.9 - 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - 0.3 - t ck positive dqs latching edge to associated clock edge t dqss - 0.27 + 0.27 - 0.25 + 0.25 - 0.25 + 0.25 t ck address and control input pulse width ( for each input ) t ipw 560 - 620 - 780 - ps ctrl, c md, addr setup to ck, ck# t is(base) 45 - 65 - 125 - ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 220 - 240 - 300 - ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max)
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical characte ristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 - cl11 10600 - cl9 8500 - cl7 parameter symbol min max min max min max unit ctrl, cmd, addr hold to c k, ck# t ih(base) 120 - 140 - 200 - ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih(1v) 220 - 240 - 300 - ps cas# to cas# command delay t ccd 4 - 4 - 4 - t ck active to active (same bank) command period t rc 48.75 - 49.5 - 50.625 - ns active bank a to active bank b c ommand t rrd max 4nck,6ns - max 4nck,7.5ns - max 4nck,7.5ns - ns active to read or write delay t rcd 13.75 - 13.5 - 13.125 - ns four bank activate period 1k page size t f aw 3 0 - 30 - 37.5 - ns 2k page size 4 0 - 45 - 50 - active to precharge command t ras 35 70200 70200 70200 t rtp max 4nck,7.5ns - max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command pe riod t rp 13.75 - 1 3.5 - 13.125 - ns load mode command cycle time t mrd 4 - 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 1 1 0 70 200 70200 70200 0 c t case 85 c t refi - 7.8 - 7.8 - 7.8 s 85 c < t case 95 c t refi it - 3.9 - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 - 300 300 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with dll off) t aonpd 2 8,5 1 9 1 9 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 1 9 1 9 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns - max 5nck,tr fc + 10ns - max 5nck,tr fc + 10ns - ns write level ling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 165 - 195 - 245 - ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 165 - 195 - 245 - ps first dqs, dqs# rising edge t wlmrd 40 - 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - 25 - t ck
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c ; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 - cl11 10600 - cl9 8500 - cl7 parameter symbol min max min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - t ck begin power supply ramp to power supplies stable t v ddpr - 200 - 200 - 200 ms reset# low to power supplies stable t rps - 200 - 200 - 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck,6ns - max 3nck,7.5ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - max 3nck, 5.625ns - t ck serial presence - detect eeprom s c l s d a s a 2 s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 2 0
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 serial presence - detect matrix byte byte description 12800 - cl11 10600 - cl9 8500 - cl7 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x11 0x10 2 dram device type 0x0b 3 module type (form factor) 0x02 4 sdram dev ice density & banks 0x02 5 sdram device row & column count 0x11 6 byte 6 reserved 0x00 7 module ranks & device dq count 0x01 8 ecc tag & module memory bus width 0x03 9 fine timebase dividend/divisor 0x1 1 0x52 10 medium timebase dividend 0x01 11 medium ti mebase divisor 0x08 12 min sdram cycle time (t ck min ) 0x0a 0x0c 0x0f 13 byte 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0xfe 0x3c 0x1c 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time (t aa min ) 0x69 17 min write recovery time (t wr min ) 0x78 18 min ras# to cas# delay (t rcd min ) 0x69 19 min row active to row active delay (t rrd min ) 0x30 0x3c 20 min row precharge delay (t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay (t ras min ) 0x18 0x20 0 x2c 23 min active to active/refresh delay (t rc min ) 0x81 0x89 0x95 24 min refresh recovery delay (t rfc min ) lsb 0x70 25 min refresh recovery delay (t rfc min ) msb 0x03 26 min int ernal write to read cmd delay (t wtr min ) 0x3c 27 min internal read to precharg e cmd delay ( t rtp min ) 0x3c 28 min four active window delay (t faw min ) msb 0x00 0x01 29 min four active window delay (t faw min ) lsb 0xf0 0x2c 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x0 1
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 byte byte des cription 12800 - cl11 10600 - cl9 8500 - cl7 32 - 59 bytes 32 - 59 reserved 0x00 60 module height (nominal) 0x0f 61 module thickness (max) 0x01 62 reference raw card id 0x00 63 address mapping edge conector to dram 0x00 64 - 116 bytes 64 - 116 reseved 0x00 117 module mfr i d (lsb) 0x83 118 module mfr id (msb) 0xda 119 module mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0xf 431 0x1fa5 0x5d0c 128 - 145 module part number "sgu01 g64a1b g 1 sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0x2c 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0xff part number code s g u 01g 64 a1 b g 1 sa - d c * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr3 - 1 6 00 mt/s sdram ddr3 240 pin u dimm chip vendor ( samsung ) c apacity (1gb yte ) 1 module rank width chip rev. g pcb - type (b63urca 0.71) chip organisation x8 * optional / additional information
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 revision history revision changes date 1 .0 initial revision 1 4 .01.2011 1. 1 new spee d - grade added (ddr 3 1600mt/s) extendet temperature - grade added (e - and w - grade) 1 1 .0 4 .201 3
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 ___________________ __________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
data sheet rev.1.1 11.04.2013 swissbit ag industriest rasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility that the product product type: 1 gb ddr3 u dimm brand name: swissmemory? product series: ddr3 u dimm part number: sg u 0 1 g64 a 1 b g 1 sa - xxxr to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restri ction of the use of certain hazardous substances 2011/65/eu swissbit ag, april 2013 manuela k?gel head of quality management

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